The present invention relates generally to semiconductor devices, and more particularly to a method to improve carrier mobility, through the incorporation of strained silicon, in semiconductor devices.
Metal-Oxide-Semiconductor field effect transistors (MOSFETs) are a common component of integrated circuits (ICs). By continually reducing the gate oxide thickness, and the length of the gate electrode, the semiconductor industry has doubled the transistor's switching speed every eighteen to twenty-four months, a phenomenon popularly known as the Moore's Law. The strategy of shrinking both the gate oxide thickness, and the source drain length, has allowed the Moore's Law to uphold in the past, but the technology market's insatiable desire for increasing switching speed is causing the strategy to reach its limits. Newer strategies, such as switching to new materials for the transistor's substrate, and the incorporation of new process methods to effectively use these new materials, are, therefore, designed and applied.
One such strategy for increasing the performance of MOSFETs is to enhance the carrier mobility of silicon (Si), thereby reducing resistance and power consumption, and increasing drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon, or strained-Si, may be formed by growing a layer of silicon on a silicon germanium (SiGe) substrate or base. The silicon germanium lattice is generally more widely spaced than a pure silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. In other words, the silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, thereby causing them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, thereby offering a potential increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without a reduction in performance.
The abruptness of the source and drain extensions is critical in strained-Si technology. One difficulty is that dopants are observed to diffuse faster in strained-Si than in Si, thereby causing drain extensions to move further under the gate and increasing gate-to-drain capacitance. Also, the diffusion of germanium across the SiGe-to-silicon boundary will release stress and reduce mobility in the strained Si layer.
In further consideration, the junction depth for source and drains should be only 35–75 nm deep for the 100 nm generation of devices to go into production in the near future, while drain extensions should only be less than 20–35 nm deep.
Therefore, desirable in the art of semiconductor designs are additional designs that may reduce the implant energy and annealing time, thereby achieving higher carrier mobility as well as shallower junctions.